Method and apparatus for partially supporting subnormal operands in

Abstract

A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency. So long as the fraction of operand permutations that occurs when a typical instruction stream is executing that are not supported in hardware is small, a performance gain is achieved. An alternative embodiment of the present invention, the gross underflow output is computed in parallel with the resulting exponent computation. An implementation of the gross underflow detection circuit can be used for either single or double precision operands.