The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 1997

Filed:

Apr. 23, 1996
Applicant:
Inventors:

Trevor K Monk, Chepstow, GB;

Andrew M Hall, Edinburgh, GB;

Assignee:

SGS-Thomson Microelectronics, Ltd., Buckinghamshire, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03B / ;
U.S. Cl.
CPC ...
331 57 ; 331 45 ; 331 74 ; 331 75 ; 331111 ; 331143 ; 3311 / ; 331D / ; 327293 ; 327295 ;
Abstract

A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage. Each of the NOR gates includes first and second input transistors that each have a control node for receiving an input signal and a controllable path between an output node and a reference voltage, a diode-connected transistor connected between the output node and the reference voltage, and a current source connected to the output node.


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