The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 1997

Filed:

Jun. 06, 1995
Applicant:
Inventor:

John P De Loe, Jr, Decatur, GA (US);

Assignee:

Oki Telecom, Suwanee, GA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ; H03L / ;
U.S. Cl.
CPC ...
331 25 ; 331 / ; 331 16 ; 331 17 ; 331D / ; 331 74 ; 327105 ; 327156 ; 327159 ; 455260 ;
Abstract

A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal.In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.


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