The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 1997

Filed:

Dec. 05, 1994
Applicant:
Inventor:

Nobuo Shiga, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03B / ;
U.S. Cl.
CPC ...
327105 ; 327113 ; 327355 ; 257280 ;
Abstract

In a mixer circuit, a first gate electrode of a dual gate MESFET having a pulse doped structure is connected through a filter to an LO signal input terminal, and a second gate electrode of the dual gate FET is connected through a matching circuit to an RF signal input terminal. The drain electrode of the dual gate FET is connected through a low-pass filter to an output terminal. The gate bias point of the first gate electrode 25a of the dual gate FET is set in the vicinity of the pinch-off point of the mutual conductance, and the gate bias point of the second gate electrode 25b of the dual gate FET is set in the area where the mutual conductance is unvaried with increase of the gate voltage. With this arrangement, the mixer circuit is so designed that the isolation characteristic of the RF signal and the LO signal is excellent, and a stable operational characteristic is obtained.


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