The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 1997
Filed:
Jun. 14, 1995
Tomomasa Ueda, Yokohama, JP;
Masahiko Akiyama, Tokyo, JP;
Atsushi Sugahara, Tokyo, JP;
Makoto Shibusawa, Odawara, JP;
Mitsushi Ikeda, Yokohama, JP;
Yoshiko Tsuji, Kawasaki, JP;
Hisao Toeda, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;
Abstract
An active matrix type liquid crystal display device having an array substrate for allowing parasitic capacitances formed between a pixel electrode and scan and signal lines disposed in the vicinity thereof to be remarkably decreased. An active matrix type liquid crystal display device is disclosed, which comprises a plurality of scan lines, a plurality of signal lines intersected with the plurality of scan lines, the plurality of scan lines being insulated from the plurality of signal lines, a thin film transistor element having a gate portion and a drain portion and disposed at each intersection of the plurality of scan lines and the plurality of signal lines, the gate portion being connected to a scan line at the intersection, the drain portion being connected to a signal line at the intersection, an array substrate formed in the intersection and having a pixel electrode, the pixel electrode being electrically connected to the source portion of the thin film transistor element, an opposite substrate having an opposite electrode opposed to the array substrate, a liquid crystal layer disposed between the array substrate and the opposite substrate, and a shield electrode disposed on the array substrate, the shield electrode being overlaid through an insulation layer with at least part of the pixel electrode and with at least part of at least either the scan line or signal line.