Digital logic output buffer interface for different semiconductor

Abstract

An input buffer circuit is implemented in a compound semiconductor technology such as Gallium Arsenide and converts silicon semiconductor logic levels such as those produced by CMOS and TTL integrated circuits and converts them to logic levels compatible with circuits manufactured in compound semiconductor technology. The input buffer employs a balanced input circuit designed to produce an output voltage representing the switch-point of the compound semiconductor technology when the voltage received from a silicon semiconductor circuit equals the switch-point of the silicon semiconductor circuit. Otherwise, the output voltage of the input buffer is proportional to the difference between the voltage received from the silicon semiconductor circuit and the switch-point of the silicon semiconductor circuit. The balanced input circuit minimizes variations in its output voltage due to variations in power supply voltage, circuit temperature and process parameters. The source-follower configuration of the balanced input also neither sources current to or sinks current from the driving silicon circuit. An output buffer circuit provides a stable high impedance tri-state output in a compound semiconductor technology by eliminating the effects of leakage current common to such technologies. The circuit employs a second pull-down transistor that sinks a small leakage current, thereby positively biasing the source of a first pull-down transistor which turns the first pull-down transistor hard.