The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 1997

Filed:

Mar. 25, 1993
Applicant:
Inventors:

Jim Childers, Fort Bend, TX (US);

Peter Reinecke, Lockhart, TX (US);

Yutaka Takahashi, Ushiku, JP;

Seiichi Yamamoto, Ibaragi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395562 ; 395800 ; 364D / ;
Abstract

Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.


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