The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1997
Filed:
Jun. 30, 1995
Applicant:
Inventors:
Miki Furuya, Saitama, JP;
Tadashi Ezaki, Tokyo, JP;
Teruhiko Kori, Kanagawa, JP;
Satoshi Tsuchiya, Kanagawa, JP;
Assignee:
Sony Corporation, Tokyo, JP;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
348465 ; 348537 ;
Abstract
Only the data sampled by a correct sampling clock is data processed. A PLL circuit 5 generates a sampling clock locked with a sync signal in a video signal and supplies to a sampling circuit 4. A lock flag indicating whether the generated sampling clock is correctly synchronized with the sync signal or not is also generated. The data multiplexed to the sync signal is sampled by the above sampling clock. The data is stored in a memory 7. The lock flag is supplied to a controller 2 and the data that is outputted from the memory 7 is made valid or invalid according to the level of the lock flag.