Method of contact formation and planarization for semiconductor processes

Abstract

A new method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device is described. Semiconductor device structures are formed in and on a semiconductor substrate. A dielectric layer is deposited overlying the semiconductor device structures. The dielectric layer is covered with a photoresist mask and partially etched into to form first openings of a first width wherein the first openings do not contact the underlying semiconductor device structures. An oxide layer is deposited over the dielectric layer and within the first openings whereby second openings are formed having a second width smaller than the first width. The oxide layer is etched away whereby the second openings are extended through the dielectric layer to the underlying semiconductor device structures to form small contact openings having the second width and whereby the dielectric layer is planarized. A conducting layer is deposited and patterned to complete the formation of the small contacts and planarized dielectric layer in the fabrication of an integrated circuit device.