The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1997
Filed:
Jul. 19, 1995
Edward D Nowak, Pleasanton, CA (US);
Subhas Bothra, San Jose, CA (US);
David Eatock, Cupertino, CA (US);
Wesley Erck, Danville, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The planarity of the dielectric layer over a processing layer is increased by adjustments made to a mask generated for patterning the processing layer. Active circuitry lines are generated for the mask. Also, a fill pattern is generated for the mask. The fill pattern is placed in areas of the mask not filled by the active circuitry lines. The active circuitry lines are combined with the fill pattern to produce a final pattern for the mask. In one embodiment, the fill pattern is generated by first over-sizing the active circuitry lines to form a first pattern. The first pattern is inverted to produce a negative of the first pattern. The negative of the first pattern serves as a marker layer. In addition, a dummy fill pattern is generated. An intersection of the marker layer and the dummy fill pattern is performed to produce an unsized fill pattern. Areas which have widths smaller than a predetermined minimum width and areas which have heights smaller than a predetermined minimum height are eliminated from the unsized fill pattern to produce the final fill pattern. The union of the original active circuitry lines and the final fill pattern forms a composite pattern for the photomask.