Performance driven bist technique

Abstract

A methodology for selecting an optimal group of flip-flops in a circuit design to be converted into BIST elements is disclosed which minimizes the performance degradation resulting from such conversion. In accordance with the present invention, the additional timing delays introduced into the circuit design resulting from each conversion of a flip-flop into a BIST element is incorporated into the selection of those flip-flops to be converted such that only those flip-flops which may be converted without any resultant timing violations are deemed suitable for conversion. A minimum group of these 'suitable' flip-flops which breaks all of the logic cycles in the circuit is then selected for BIST conversion. Thus, selection methodologies in accordance with the present invention not only simultaneously minimizes the increase in silicon area due to BIST conversion while maximizing fault coverage, but also results in minimal performance degradation.