The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 1997
Filed:
Mar. 28, 1995
Billy J Knowles, Kingston, NY (US);
Clive A Collins, Poughkeepsie, NY (US);
Christine M Desnoyers, Pine Bush, NY (US);
Donald G Grice, Kingston, NY (US);
David B Rolfe, West Hurley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each of the nodes provides a functional unit with a processor, shared memory, and communication interface. K zipper ports in addition provide a switching function to interconnect the distributed memory and processors providing the shared memory. The resulting multi-ported shared intelligent memory switch can be used to connect (switch) a variety of computer system elements (CSEs) including computers and direct access storage devices (DASDs). The multi-ported intelligent memory shared memory organized into a collection of cells or nodes and is called the hedgehog. Each node comprises a finite computer memory, a processing unit, and communication interface and at least K of the nodes of the device have a zipper port. The computing system element combines the characteristics of a switch with those of a shared memory. In addition, objects in the shared memory can change state without the intervention of computing system elements (CSEs) that are interconnected to the device (CSE and port) which is a hedgehog switch. A zipper and ISA architecture for the chip are described for implementation of the zipper node of the shared memory device.