The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 1997

Filed:

Jun. 06, 1995
Applicant:
Inventor:

Hanumanthrao Nimishakavi, Fremont, CA (US);

Assignee:

Cirrus Logic, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375376 ; 327156 ; 327160 ;
Abstract

A digital phase-locked loop for receiving an encoded stream of data and generating a receive clock signal therefrom is provided with a counter, such as a down counter, having an adjustable start count value. An edge detector detects the rising and falling edges within a stream of data. The detection of an edge causes the counter to start counting from the start count value towards a terminal value. A receive clock generator is provided that generates a receive clock signal, the receive clock generator being responsive to the counter reaching at least a first predetermined value to change a level of the receive clock signal. The use of a down counter that is loaded with a start count value upon the detection of an edge provides fast re-synchronization when an edge has been missed, while providing accurate recovery of the clock from the encoded stream of data.


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