Apparatus for retiming digital data transmitted at a high speed

Abstract

This invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting local clock pulse FT; delayed clock pulse parallel generation means 12 for outputting, in parallel, n delayed clock pulses delayed sequentially by one cycle of local clock pulse FT; input data transition detection means 13 for outputting pulse DT each time the rising and falling carrier waves intersect in input data D; sequential logic parallel phase detection means 14 for providing clock pulse selection data by outputting sequential logic phases of the upper location of the pulse generated during input data transition and transition location of n delayed clock pulses; retiming clock pulse selection means 15 for outputting a retiming clock pulse according to the clock pulse selection data of the input delayed clock pulses; time delay compensation means 16 for outputting delayed input data; and data retiming means 17 for outputting the data retimed DR according to the retiming clock pulse.