Integrated circuit memory having high speed and low power by selectively

Abstract

A memory in an integrated circuit chip includes an array of memory cells and a read/write circuit which performs precharge and sense operations on the array for a time interval that is set by the width of a pulse signal. This pulse signal is generated by a pulse generator circuit which contains transistors that switch on and off at an unpredictable speed; and consequently, the width of the pulse signal has a large tolerance. To decrease this large tolerance in the pulse signal, a compensation circuit is provided which includes a plurality of compensation components for the pulse generator. This compensation circuit selectively couples the compensation components to the pulse generator such that the selectively coupled components in combination with the pulse generator's transistors produce the pulse signal with a precise width that has an insignificant tolerance.