The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 1997

Filed:

Apr. 20, 1994
Applicant:
Inventors:

Mehdi Katoozi, Bellevue, WA (US);

George S La Rue, Bellevue, WA (US);

Assignee:

The Boeing Company, Seattle, WA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 41 ; 323283 ;
Abstract

A control for a pulse width modulated power supply. The control (14) uses a digital pulse width modulator (48, 48') to produce set and reset signals that determine the duration of control pulses supplied to the pulse width modulated power supply (12). In one embodiment, a plurality of analog-to-digital converters (50, 51, 53) convert analog signals indicative of different parameters monitored on the pulse width modulated power supply to digital values. Differences between the digital values and corresponding predefined desired reference values are determined, combined, and the result is input to a digital comparator (72) of the digital pulse width modulator. The digital comparator produces a reset signal when the combined differences equal a count of clock pulses accumulated on a counter (76). A second digital comparator compares the count to a predefined count and produces a set signal when the two digital values are equal. The set and reset signals are applied to a flip-flop (88) to produce the control pulses, and the set signal resets the counter to initiate the next count cycle. In a silicon CMOS embodiment having a limited switching frequency capability, the required resolution is achieved by using a vernier (94) to incrementally delay the reset signal based upon the least significant bits of the difference signal.


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