Clock deskewing apparatus including three-input phase detector

Abstract

A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances. A three input phase detector is coupled to a fixed delay line and to either the series terminated transmission line system or the Thevenin terminated transmission line system for eliminating phase shifts of the clock signals between the different loads.