The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 1997
Filed:
Apr. 07, 1995
Applicant:
Inventors:
Richard D Freeman, San Carlos, CA (US);
Joseph D Linoff, San Jose, CA (US);
Timothy Saxe, Los Altos, CA (US);
Assignee:
Zycad Corporation, Fremont, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 39 ; 326 41 ;
Abstract
The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.