The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 1997
Filed:
Nov. 18, 1994
Young S Kwon, Inchon-jikal, KR;
Seung H Ahn, Suwon, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A semiconductor device having at least one semiconductor chip loaded on a lower surface of a printed circuit board, electrode terminals of the semiconductor chip wire-bonded to terminals on the printed circuit board, and a connection portion of the semiconductor chip and wires encapsulated by means of encapsulating resin includes a semiconductor device of three-dimensional structure having the printed circuit board reversely mounted, the terminals of the printed circuit board connected to external terminals via through holes, and at least one semiconductor device stacked on an upper surface of the printed circuit board, thereby interconnecting respective semiconductor devices while interposing solder balls to be mounted to other printed circuit boards by leads being the external terminals. Thus, a ball grid array (BGA) package able to be stacked inside a small out-line J-lead (SOJ) package is used for performing interconnection to make the BGA overcome a typically two-dimensional flat mounting and attain a three-dimensional surface mounting structure while being perfectly compatible with a currently-available mounting process on the main substrate, thereby improving mounting efficiency.