Cache memory utilizing address translation table

Abstract

A method for operating a cache memory system has a high speed cache memory and a mass storage device operates in a highly efficient manner with a host device. The method operates to dynamically assign segments of the cache memory to correspond to segments of the mass storage device, accept data written by the host into portions of the assigned segments of the cache memory, determines if the elapsed time since any modified data has been written to the cache memory exceeds a predetermined period of time, or if the number of modified segments exceeds a preset limit. If so, the cache memory system enables a transfer mechanism to cause modified data to be written from the cache memory to the mass storage device, based on the location of segments relative to a currently selected track of the mass storage device. Movement of updated data from the cache memory (solid state storage) to the mass storage device (which may be, for example, a magnetic disk) and of prefetched data from the mass storage to the cache memory is done on a timely, but unobtrusive, basis as a background task. A direct, private channel between the cache memory and the mass storage prevents communications between these two media from conflicting with transmission of data between the host and the cache memory system. A set of microprocessors manages and oversees the data transmission and storage. Data integrity is maintained in the event a power interruption via a battery assisted, automatic and intelligent shutdown procedure.