The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 1996
Filed:
May. 24, 1995
Sunil Mirapuri, Mountain View, CA (US);
Thomas J Riordan, Los Altos, CA (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
A method and apparatus for restarting an instruction processing pipeline after servicing one or more interlock processing faults. A pipeline architecture is defined in which processing interdependencies (such as instruction latencies, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present so as to increase pipeline throughput. Interdependencies which actually occur appear as processing faults which then are serviced. At the completion of the servicing, pipeline restarting operations occur, during which the portions of the pipeline which are invalidated are preloaded. Preloading includes backing-up the invalidated stages and re-executing such stages with corrected information so as to fill the pipeline. The pipeline portions (e.g., stages) which are invalidated are determined by the type of processing fault which occurs. Upon completion of preloading, normal instruction pipeline processing resumes.