Method and apparatus for the pipelining of data during direct memory

Abstract

A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data transmitted across the external bus from an external device, and forwards the data onto the memory bus for transfer to the memory. Similarly, the bus controller receives data to be written to external device from the memory and transfers it across the external bus to the external device. The bus controller includes logic to detect burst transfers and word alignment to determine the minimum number of words that can be transferred across the memory bus while the data transfer from the external device is ongoing. Therefore, instead of waiting for the entire block of data to be received into the processor before transferring it to the memory, portions of the block transferred, for example, two words at a time, are transferred to the memory, while additional data is being received at the processor. If two words are transferred at a time across the memory bus, then at the end of a block transfer only one additional cycle is required to transfer the last two words of data to the memory. Similarly, for a write operation to the external device, data can be piecewise transferred across the slower external bus as it is received in the bus controller in order to minimize the time required to complete the transfer.