Method for testing an electrically erasable and programmable memory

Abstract

A method for testing an electrically erasable and programmable memory device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, comprises the steps of: programing all the memory cells of the memory device; submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; reading the information stored in all the memory cells of the memory device; memorizing the addresses of defective memory cells which have been read as erased memory cell; storing the addresses of the defective memory cells in redundancy registers associated to redundancy memory cells which must substitute the defective memory cells.