The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 1996
Filed:
Jun. 07, 1995
Kirk D Peterson, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A current mirror circuit (40) includes a first pair of mirrored transistors (T.sub.1 and T.sub.2) having common gate and source connections; a second pair of cascoded transistors (T.sub.3 and T.sub.4) with common gate connections, respectively connected in series between the first pair transistors (T.sub.1 and T.sub.2) and input and output voltage terminals (+V.sub.IN and +V.sub.OUT). First and second voltage level shifter circuitries (41,42) establish shifted bias voltages respectively at the first and second pair transistor gate connections. The first voltage level shifter comprises a pair of transistors (T.sub.5 and T.sub.6) connected in series between an applied voltage terminal and the second pair transistor source connections, for establishing a shifted biasing voltage at the second pair transistor gate connection. The second voltage level shifter comprises a pair of transistors (T.sub.7 and T.sub.9) connected in series between the applied voltage terminal and the first pair transistor source connections, for establishing a bias voltage at the first pair transistor gate connections.