The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 1996

Filed:

Dec. 20, 1994
Applicant:
Inventor:

Hitoshi Araki, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257316 ; 257326 ; 36518517 ;
Abstract

The structure of the invention employs a lamination type memory cell and a lamination type select transistor having a floating gate. Since no contact holes are formed in a first polysilicon film of a high resistance, it is not necessary to form a contact hole in the gate wire of the select transistor between a cell array. A floating gate is beforehand charged with electricity so that the select transistor cab have a positive threshold value. Alternatively, an impurity is introduced into the channel region of the select transistor so that the neutral threshold voltage of the transistor after radiation of ultraviolet rays can have a positive value.


Find Patent Forward Citations

Araki, Hitoshi. (1996). Electrically erasable programmable non-volatile semiconductor memory (U.S. Patent No. 5589699). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5589699

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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