The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 1996

Filed:

Jul. 15, 1994
Applicant:
Inventor:

N Deepak Swamy, Austin, TX (US);

Assignee:

Dell USA, L.P., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
361777 ; 361760 ; 361772 ; 361773 ; 361792 ; 361801 ; 174260 ; 257727 ;
Abstract

To facilitate the registered connection between a laminated multi chip module and an associated multi-tiered circuit board, spaced series of vias are formed transversely through the circuit board and module substrates between their opposite first and second sides. Gold plated BGA leads, offset from the module substrate vias, are formed on the first module substrate side on multi-layer plating structures disposed thereon and extending along the module via interior side surfaces. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the circuit board vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped BGA leads of the multi chip module, and are positioned on the same centerline pattern as the leads. After the circuit board vias and sockets are formed, a multi-layer metallic coating is deposited on their interiors and around their open ends on the first board side, with the coating being extended across the first board side between associated socket and via pairs. Like the BGA leads, this coating has a gold outer layer. The multi chip module is placed against the first circuit board side in a manner causing the BGA leads to partially enter the plated sockets, and a resilient clamping structure is used to releasably hold the BGA leads in their associated metal-coated sockets.


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