The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 1996

Filed:

Sep. 02, 1993
Applicant:
Inventors:

Francis E Froebel, Essex Junction, VT (US);

David L Gardell, Fairfax, VT (US);

Gary H Irish, Jericho, VT (US);

Mohammed S Shaikh, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
174 524 ; 257666 ; 257667 ; 257789 ;
Abstract

The present invention provides a method for forming an improved lead-on chip semiconductor module and an improved module of this type. In a lead-on chip semiconductor device, a semiconductor chip which has a major surface having input and output bonding pads thereon, is secured to a lead frame having a plurality of leads adjacent the bonding pads by means of bonding wires connecting a respective one of the leads to a pad on the chip. A coating of dielectric material having a Young's modulus in the range of about 10 psi to about 500 psi is disposed around the entire length of each of the wires and over the pads and over the portion of the respective leads to which the wires are connected to act as a stress buffer. This material preferably has a T.sub.g of at least as low as -40.degree. C. Also preferably this package is encapsulated with conventional encapsulant.


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