The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 1996

Filed:

Nov. 29, 1993
Applicant:
Inventors:

Hideaki Yamamoto, Tokorozawa, JP;

Haruo Matsumaru, Tokyo, JP;

Yasuo Tanaka, Tokyo, JP;

Ken Tsutsui, Tokyo, JP;

Toshihisa Tsukada, Tokyo, JP;

Kazuo Shirahashi, Mobara, JP;

Akira Sasano, Tokyo, JP;

Yuka Matsukawa, Mobara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437 51 ; 437194 ; 437246 ;
Abstract

The present invention concerns an active-matrix addressed TFT substrate using a thin film transistor, a manufacturing method and an anodic oxidation method thereof, a liquid crystal display panel using the TFT substrate and a liquid crystal display equipment using the liquid crystal display panel and, more in particular, it relates to a structure and a manufacturing method which enables to improve the characteristics thereof. In the present invention, Cr or Ta is used for gate terminals, aluminum or a metal mainly composed of aluminum is used for gate bus-lines extended therefrom, gate electrodes and thin film capacitances (additional capacitance, storage capacitance) and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulation films for the intersections between the bus-lines. In a more preferred structure, the anodic oxidized film is used for all of the gate insulators, the dielectric films for the thin film capacitances and the interlayer insulation films for the intersections between the bus-lines.


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