The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 1996

Filed:

Dec. 09, 1994
Applicant:
Inventors:

Hoichi Cheong, Austin, TX (US);

Dwain A Hicks, Pflugerville, TX (US);

Kimming So, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395449 ; 395446 ; 395448 ; 395451 ; 395457 ; 395463 ; 36424345 ; 36424612 ; 364964343 ; 3649662 ; 364D / ; 364D / ;
Abstract

The present invention provides balanced cache performance in a data processing system. The data processing system includes a first processor, a second processor, a first cache memory, a second memory and a control circuit. The first processor is connected to the first cache memory, which serves as a first level cache for the first processor. The second processor and the first cache memory are connected to the second cache memory, which serves as a second level cache for the first processor and as a first level cache for the second processor. Replacement of a set in the second cache memory results in the set being invalidated in the first cache memory. The control circuit is connected to the second level cache and prevents replacing from a second level cache congruence class all sets that are in the first cache.


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