Control systems having an address conversion device for controlling a

Abstract

A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.