Addressing scheme for microcode store in a signal processor

Abstract

When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes for each arriving signal unit. To generate the cycle, the signal processor contains base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N). The base address reproducing means feed microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). Selection is implemented by adding each base address BA(i) to an associated index IA(i), determined in dependence on signal data received from the processing circuitry. Usually, the indices IA(i) require fewer bits than the base addresses BA(i); the indices are determined in codependence of the base address, or of a signal identifying a class to which the base address belongs. The signal data is collected from the processing circuitry via a shift register.