The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 1996
Filed:
Dec. 21, 1994
Satoshi Kobayashi, Kamakura, JP;
Toshikazu Yokoi, Kamakura, JP;
Kunio Takahari, Kamakura, JP;
Yoichi Nakamura, Kamakura, JP;
Junichi Ishikawa, Kamakura, JP;
Nigel Bruce, Birmingham, GB;
David Wright, Birmingham, GB;
Colin Hough, Birmingham, GB;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Apricot Computers Limited, Birmingham, GB;
Abstract
A symmetric multiprocessor system connecting a plurality of CPUs by a common bus initializes itself while defective CPUs are set aside to use only the remaining CPUs when the power is turned on, thereby maintaining the predetermined CPU numbers and giving a minimum influence with the existing software thereof. The multiprocessor system includes an identifier setting register to designate in a predetermined order the CPU numbers only to normal CPUs, and a reset controller to cut off the defective CPUs from the common bus. The multiprocessor system can automatically start re-setting up where the defective CPUs are detected during the processing of setting-up based on the time-out detection, can release an abnormal state of the hardware, and can control the setting-up processing in use of any CPU based on the level of a reset status input port and contents of a reset information register.