The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 1996
Filed:
Jun. 21, 1994
Sumitaka Takeuchi, Itami, JP;
Toshio Kumamoto, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D.sub.1a, D.sub.1b) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D.sub.1b, D.sub.1c) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is 'L' if all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D.sub.1c) at its input. When all of the A-D converters are normal, all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.