Internal clock signal generation circuit having external clock detection

Abstract

An internal clock generation circuit is provided for receiving an external clock signal. Based upon the duration of each high and low pulse width of the external clock signal, the internal clock generation circuit selects one of two possible clock signals as an internal clock signal for connection to a load device. Selection is based upon whether the high and low pulse durations of the external clock signal exceed or are less than a threshold amount. If exceeded, the external clock signal connects a longer duration pulse width internal clock signal to the load device. If less than, the internal clock signal connects a shorter duration internal clock signal to the load device. Accordingly, the internal clock generation circuit allows for variability in the external clock signal frequency and duty cycle and correspondingly selects one of two (and possibly more) clock signals for connection to the load device. Detection and selectability allows for load device operation at speeds less than maximum designed amounts in order to salvage slower speed devices and improve wafer yield.