Tri-directional buffer

Abstract

A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line. The novel buffer is configurable to realize any of the above configurations using programmable memory cells and therefore is well suited for application within a programmable integrated circuit. Since the novel buffer utilizes only a single pair of inverters to provide the buffering, in any configuration, it does not contain unused driver circuitry when configured. Therefore, the novel buffer advantageously consumes a relatively small amount of substrate area.