The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 1996

Filed:

Jul. 26, 1994
Applicant:
Inventor:

Roger S FitzPatrick, Cheltenham, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395500 ; 364D / ; 364D / ; 364578 ; 39518309 ;
Abstract

A dual lane computing system has at least one processor in each lane, each processor having an associated store which stores input data supplied to the processor and their time of arrival. The lanes produce nominally-identical outputs which are supplied to a comparator that detects when there is a discrepancy between the lanes. When a discrepancy is detected, an external processor is loaded with software that simulates the operation of the lanes. The data in the store associated with one of the lane processors is supplied to the simulator processor in respect of the input just prior to the detection of the discrepancy. The simulator simulates the operation of one lane utilizing this data and its output is compared in the comparator with the actual output of that lane as recorded when the discrepancy occurred.


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FitzPatrick, Roger. (1996). Two lane computing systems (U.S. Patent No. 5581739). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5581739

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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