The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 1996

Filed:

May. 15, 1995
Applicant:
Inventors:

Toshiyuki Furuta, Yokohama, JP;

Hiroyuki Horiguchi, Yokohama, JP;

Hirotoshi Eguchi, Yokohama, JP;

Yutaka Ebi, Yokohama, JP;

Tatsuya Furukawa, Yokohama, JP;

Yoshio Watanabe, Kawasaki, JP;

Toshihiro Tsukagoshi, Itami, JP;

Assignee:

Ricoh Company, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395 27 ; 395 11 ; 395 24 ; 395 26 ;
Abstract

A hierarchical signal processing apparatus includes aggregates having logic operation portions. The apparatus compares a final output signal from a logic operation portion in a final aggregate with a teaching signal, and generates an error signal by taking a signal which exists only in the teaching signal as a positive error signal, and taking a signal which exists only in said final output signal as a negative error signal. An error signal generating portion in the apparatus generates a positive error signal of a logic operating portion within a certain aggregate which supplies one or more output signals thereof to said logic operation means of another aggregate based on one or more logic operations on the excitatory weight function signal of said weight function signal, the positive error signal, the inhibitory weight function signal of said weight function signal and the negative error signal, and also generates a negative error signal of said logic operation means within said certain aggregate which supplies one or more output signals thereof to said logic operation means of said other aggregate based on one or more logic operations on the inhibitory weight function signal of said weight function signal, the positive error signal of said other aggregate, the excitatory weight function signal of said weight function signal and the negative error signal.


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