Bufered intelligent digital tape controller with onboard ecc and

Abstract

A buffered computer data storage tape controller having a microprocessor, a buffer memory, a host interface, an error correction circuit, and a tape drive interface. A host interface control program executed by the microprocessor controls the host interface for transferring computer data between the buffer memory and a host computer, and for receiving commands from the host computer. An error correction circuit control program executed by the microprocessor controls the error correction circuit for generating parity information for computer data stored in the buffer memory and to be written to tape, and for providing error correction for computer data storage read from tape and stored in the buffer memory for transfer to the host computer. A tape interface control program executed by the microprocessor controls the tape drive interface for transferring computer data between the buffer memory and a tape drive. The control programs are configured to suspend execution at predetermined suspend points and to continue execution at return points associated with said suspend points, and are executed sequentially in a concurrent manner by a scheduler program so that execution of the next control program in sequence continues when an executing program suspends. Interrupt routines executed pursuant to interrupts are provided for accomplishing tasks that have high priority.