The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 1996
Filed:
Jul. 06, 1994
Shigeto Mizukami, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor integrated circuit device, comprises: an n.sup.+ -type buried layer 12 formed on a surface of a p-type semiconductor substrate 11; an n-type semiconductor layer 71 formed on the n.sup.+ -type buried layer 12; a first p type well 16 formed in the semiconductor layer 71; a second p-type well 18 formed in the semiconductor layer 71 and electrically isolated from the first p-type well 16; an input-protecting N-type MOS transistor 102 formed in the first p-type well 16 and having a drain 22 grounded, a source 25 connected to an input terminal 101 to which an external signal is input, and a gate 23 grounded; and an n.sup.+ -type impurity region 27 grounded and formed in the second p-type well 18. Whenever a negative surge voltage is applied to the input terminal 101, a current path is formed from the ground V.sub.SS to the input terminal 101, by way of the impurity region 27 formed in the second p-type well 18, the n.sup.+ -type buried layer 12, and the source 25 formed in the first p-type well 16, in addition to the current path through the input-protecting N-type MOS transistor 102 formed in the first p-type well 16, thus improving the input-protection characteristics of the circuits formed in the same semiconductor substrate against a surge voltage applied to the input terminal 101.