Repetitive digital sampling circuit using two delay lines for improved

Abstract

A digital sampling circuit is providing for repetitively launching a series of stimulus pulses into a network under test and digitally sampling the resulting response signal. Enhanced time base accuracy of the repetitive sample is obtained using a pulse delay line in series with the pulse generator and a sample delay line in series with sample-and-hold (S/H) circuit. By summing digital samples obtained for the same time delay but using unique combinations of pulse delay line and sample delay line whose absolute time errors are combined differentially, the absolute time delay error contributed by both delay lines appears as a constant systematic error for any selected point along the response signal, allowing for highly accurate time intervals between selected points. This architecture is used to obtain an equivalent sampling resolution of 2 nanoseconds because each of the delay lines has two nanosecond steps. The summing process of the dual delay line architecture allows off-the-shelf delay lines with absolute accuracy specified at .+-.1 nanosecond to be accommodated.