The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 1996
Filed:
Dec. 27, 1994
Applicant:
Inventor:
Kouichi Hirosawa, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B05D / ;
U.S. Cl.
CPC ...
427 97 ; 427 98 ;
Abstract
A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.
Hirosawa, Kouichi. (1996). Method of manufacturing printed circuit board by a build-up technique (U.S. Patent No. 5578341). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5578341
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile