The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 1996
Filed:
Dec. 28, 1994
Owen S Bair, Saratoga, CA (US);
Adam Kablanian, San Jose, CA (US);
Charles Li, San Jose, CA (US);
Farzad Zarrinfar, Pleasanton, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.