The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 1996

Filed:

May. 22, 1995
Applicant:
Inventor:

Larry B Phillips, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327202 ; 327203 ; 327208 ; 327211 ;
Abstract

A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively. In the illustrative embodiment, the second circuit is an arrangement which includes a first switching element with a first terminal connected to a first node, a control terminal responsive to the first intermediate complementary output signal and a third terminal for providing a third intermediate complementary output signal. The second circuit includes a second switching element having a first terminal connected to the first node, a control terminal responsive to a second complementary input signal and a third terminal for providing a fourth intermediate complementary output signal. The second circuit further includes a third switching element having a first terminal connected to the first node, a second terminal connected to a source of supply and a control terminal connected to a source of a clock signal.


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