Mis capacitor and a semiconductor device utilizing said mis capacitor

Abstract

The present invention discloses the structure of a MIS capacitor adapted to be interposed between two terminals, i.e., first and second terminals, to be connected to an electric circuit. Formed on a common semiconductor substrate are first and second capacity insulator layers, first and second electrically conductive layers thereon, and first and second impurity diffusion areas under the first and second capacity insulator layers. Also formed are a first wiring line which connects the first electrically conductive layer and the second impurity diffusion area to the first terminal, and a second wiring line which connects the second electrically conductive layer and the first impurity diffusion area to the second terminal. Accordingly, the first electrically conductive layer and the second impurity diffusion area form one electrode, while the second electrically conductive layer and the first impurity diffusion area form the other electrode. With the arrangement above-mentioned, voltage dependencies inherent in capacitors each having a MIS structure are substantially cancelled with each other, resulting in reduction of the voltage dependency of the MIS capacitor. Through a process using one polysilicon layer, there can be formed an economical MIS capacitor having a small area which can be mounted on an analog circuit.