Modular buffer memory with separately controllable logical output queues

Abstract

A modular system for a buffer memory used for storing output queues (80a-k) of a packet switch is described. A series of memories (90) are each connected to both the input lines (10a-k) and the output lines (160a-k) of the switch. Each memory (90) is provided with a memory controller (100) connected to a latch (50) which is in turn connected to AND gates (60a-k). These AND gates (60a-k) ensure that packets are only stored in the memory (90) of the module in which the first latch (50) is set. When the memory (90) is full, the memory controller (100) resets this first latch (50) in the current module and sets the corresponding first latch (50) in the next module. The packets are then read into the memory (90) of the next module. A marker circuit (70) is used to insert in the output queues (80a-k) a marker to indicate that the next entries of the queue are to be found in the next module. On reading out the packets, this marker is detected by a detector (110a-k) which then resets a second latch (140a-k) in the module from which the packets are currently being read and sets a corresponding second latch (140a-k) in the next module. AND gates (150a-k) ensure that packets are only read out of those output buffer queues (80a-k) whose corresponding second latch (140a-k) is set. Each of the switch output lines (160a-k) can therefore only receive packets from one module. Different switch output lines (160a-k) will, however, receive packets from different modules.