The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 1996
Filed:
Sep. 09, 1994
Osamu Ishikawa, Tokyo, JP;
Toshikazu Ito, Tokyo, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
A DRAM control circuit according to the present invention, comprising a DRAM, a DRAM controller adapted for receiving an address, write data, and a data rewrite command from a host controller and designating a row address and a column address to the DRAM, and a column address strobe signal control circuit, causes pseudo column address strobe signal DCASq-N to have 'L' level to read the contents of the address when column address strobe signal DCAS-N and read signal RD-N have 'L' level, causes pseudo column address strobe signal DCASq-N to have 'H' level to set an input/output terminal I/O to high impedance when the read signal RD-N has 'H' level, further causes pseudo write signal WR-q to have 'L' level to output write data to a data bus when the input/output terminal I/O remains at the high impedance, and rewrites the contents of the address to the write data when the pseudo column address strobe signal DCASq-N is caused to have 'L' level.