Bussed test access port interface and method for testing and controlling

Abstract

Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line. If the instructions or data are intended for a specific system logic board, its corresponding ME signal line will be enabled to permit the passage of these signals and the resulting TDO signal through the interface enable circuit. This arrangement permits the incorporation of a bussed TAP interface into a system control interface for testing and controlling system logic boards that comply fully with the IEEE 1149.1 standard, while conserving the system controller card backplane pins dedicated to TAP signals, to two pins per system logic board plus four pins for the bussed TAP interface.