The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 1996

Filed:

Nov. 29, 1994
Applicant:
Inventor:

Menahem Lowy, Arlington, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364717 ;
Abstract

A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.


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Lowy, Menahem. (1996). Parallel architecture for generating pseudo-random sequences (U.S. Patent No. 5574673). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5574673

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