The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 1996

Filed:

Nov. 17, 1995
Applicant:
Inventors:

Louis L Hsu, Fishkill, NY (US);

Mary J Saccamango, Poughquag, NY (US);

Joseph F Shepard, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437162 ; 437164 ;
Abstract

A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.


Find Patent Forward Citations

Hsu, Louis. (1996). Method of making thin film transistor with a self-aligned bottom gate (U.S. Patent No. 5573964). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5573964

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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