The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 1996
Filed:
Nov. 29, 1994
John G Gore, Sorrento, FL (US);
Sawtek, Inc., Orlando, FL (US);
Abstract
A hidden lead package device is configured to be placed between a leadless component such as a surface mount package (SMP) used to house a SAW device and a standard printed circuit board configured for solder joints in a leadless contact with the printed circuit board. The hidden lead device is made using materials having similar characteristic thermal expansion properties as that of the SMP and printed circuit board pads to which the hidden lead is affixed. The hidden lead extends across the underside of the SMP along the PCB surface. One end of the lead is brazed to an SMP pad and the opposite end is soldered to a communicating PCB pad. The brazing temperature is higher than the reflow temperature for the solder. The hidden lead device causes the relative movement between the leadless carrier and the printed circuit board to occur along a length of the hidden lead and thus minimizes tensional or compressive forces to the solder joints. Such an approach relieves the stress and resulting creep typically seen at solder joints when mounting leadless packages to printed circuit boards. In addition, by segregating the input and output pads and placing the hidden leads to ground pads between those of input and output pads, crosstalk rejection of the components is improved.